A phase-locked loop (PLL) circuit automatically adjusts a clock signal derived from a voltage controlled oscillator (VCO) until it matches the phase and frequency of a reference clock signal. In frequency lock mode, an adaptive frequency calibration (AFC) circuit compares the frequency of a reference signal with that of a feedback clock signal. After comparing the signals, the AFC can output control bits to adjust the frequency of a VCO output signal. For example, U.S. Pat. No. 7,154,348 to Lee et al., entitled “Frequency Synthesizer Using a Wide-Band Voltage Controlled Oscillator and a Fast Adaptive Frequency Calibration. Method,” discloses an AFC circuit which compares the frequency of an output signal of a VCO with an input signal and outputs control bits to the VCO based on the comparison. The VCO of such a frequency synthesizer has a plurality of operating characteristic curves associated therewith. In response to the AFC's control bits, which are output as a result of the signal comparison, the VCO selects one of the plurality of operating characteristic curves, where each operating characteristic curve corresponds to a different control word. After determining the control word and corresponding operating characteristic curve in frequency lock mode, the frequency synthesizer adjusts the phase of the VCO while moving along the selected operating characteristic curve in phase lock mode.
Frequency locking time plays an important role, for example, in radio frequency (RF) synthesizer applications such as wireless communications. As the frequency range covered by a synthesizer increases, the number of VCO operating characteristic curves (or sub-bands) also increases, thus prolonging synthesizer locking time. That is, the broader frequency range translates into a longer time for the VCO output signal to match the frequency of the reference signal. More precisely, the dominant locking time in frequency lock mode is the amount of time needed for the AFC circuit to search for control bits to control the VCO. As illustrated in FIG. 2A, using AFC multi-bit control words cw[k] with k bits, AFC circuits may require as many as 2k−1 frequency comparisons to generate control bits for a target multi-bit control word cw[k] for VCO band selection. This type of algorithm starts with a given multi-bit control word cw[k], such as 0000, and then iteratively searches through other multi-bit control words cw[k] until finding the target multi-bit control word cw[k]. Such AFC circuits do not wholly meet the requirements of various applications using wide frequency ranges but requiring fast locking times.